1. Field of the Invention
The present invention relates to tests of integrated circuits. More particularly, the present invention relates to a structure of a test key for checking an interconnect structure, and to a method for checking an interconnect structure using the test key.
2. Description of the Related Art
In a multi-level interconnect process of a semiconductor process, many test key are usually formed in the scribe line regions of the wafer for checking the electrical connections between the conductive plugs and the overlying and underlying conductive lines of the interconnect structure.
FIG. 1 illustrates a prior-art test key and a corresponding interconnect structure. The interconnect structure and the test key 106 are formed in a device area 102 and in a scribe line area 104, respectively, of a substrate 100. The test key 106 is constituted of lower metal layers 110b, plugs 150b and upper metal layers 160b. The upper and lower metal layers 110b and 160b are arranged alternately, wherein each upper (lower) metal layer 160b (110b) is connected to two lower (upper) metal layers 110b (160b) via two plugs 150b to form a contiguous conductive structure.
The metal layers 110b are formed simultaneously with the lower metal layers 110a, the plugs 150b are formed together with the plugs 150a, and the metal layers 160b are formed together with the upper metal layers 160a of the interconnect structure. Usually, after the metal layers 110a/b are formed, a thin oxide layer 120 is formed all over the substrate 100, the gaps between the metal layers 110a/b is filled with spin-on glass (SOG) 130, and then an oxide layer 140 is formed covering the metal layers 110a/b and the SOG 130. Thereafter, via holes 146a/146b are formed in the oxide layer 140 in the device area 102/scribe line area 104 and then filled with metal to form plugs 150a/150b. In addition, as shown in FIG. 2, to make the metal filling easier, a wet etching step using buffered oxide etchant (BOE) and using the photoresist patterns 142 for defining the via holes 146a/b as a mask is usually conducted before the via holes 146a/b are defined to form wider cavities 144a/b above the via holes 146a/b. 
To check the interconnect structure, the electromigration (EM) destruction time of the test key 106 can measured. If the plugs 150a of the interconnect structure have defects, the plugs 150b formed simultaneously with the plugs 150a should also have defects. Thus, the EM destruction time of the test key 106 will be reduced allowing the problem to be detected.
However, the problems of the metal layers 110a cannot be reflected by the conventional test key 106. For example, when the gap between two metal layers 110a is overly narrow or the gap-filling property of the raw material of the SOG 130 is poor, a seam 133 (FIG. 2) easily occurs in the SOG 130 and extends through the oxide layers 120 and 140 so that the metal layers 110a are corroded in the BOE etching for forming the cavities 144a/b, as shown in FIG. 2. Such corrosion of the metal layers 110a cannot be indicated by using the conventional test key 106.